1. Technical Field
The present disclosure relates to display signal transmission, and more particularly, an apparatus and method for transmitting a display signal having a protocol which includes a dummy signal and a clock signal.
2. Related Art
A flat panel display device transmits a display signal including image data to a display panel, and displays an image corresponding to the image data on the display panel.
The flat panel display device may be configured to transmit a display signal through PPDS (Point-to-Point Differential Signaling), RSDS (Reduced Swing Differential Signaling), or mini-LVDS (mini Low Voltage Differential Signaling).
The PPDS is vulnerable to EMI (Electromagnetic Interference), and may cause a data sample error when a skew exists between a clock signal and image data which are transmitted through different transmission lines. The mini-LVDS and RSDS are configured to separately transmit image data and a master clock signal for recovering the image data. The mini-LVDS and RSDS may cause a signal distortion due to a reflected wave which is generated by impedance mis-match of a transmission line for transmitting the master clock signal, and are vulnerable to EMI.
In order to solve the above-described problems, a protocol having a clock signal embedded in image data has been proposed. In this case, the image data and the clock signal are transmitted through the same transmission line, and the protocol is referred to as CEDS (Clock Embedded Data Signaling).
However, the conventional CEDS protocol needs to secure a sufficient margin before and after the point of time that a clock signal is extracted between image data, in order to deal with a high-frequency operation.
In the conventional CEDS protocol, the edge of a time point at which a clock signal is extracted is pinned to a rising or falling edge. Thus, a dummy signal which is positioned after the last bit of the image data must transition to the pinned edge state for extracting a clock signal.
When the dummy signal is pinned to a high level and the last bit of the image data is at a low level or when the dummy signal is pinned to a low level and the last bit of the image data is at a high level, a level difference exists between the last bit of the image data and the dummy signal. Thus, a level transition may occur between the last bit of the image data and the dummy signal. The level transition which occurs before the dummy signal may occur for each of the image data.
That is, in the conventional CEDS protocol, a level transition may occur between the last bit of the image data and the dummy signal. As a result, the dummy signal which is pinned to extract the clock signal may periodically cause EMI on a basis of image data.